1. Field of the Invention
The present invention relates to lithographic processing cells, comprising a lithographic apparatus and a track apparatus, and associated device manufacturing methods.
2. Description of the Related Art
Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a patterning device may be used to generate a desired circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist).
In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion in one go, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the projection beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
In a factory, commonly referred to as a “fab” or “foundry”, in which semiconductor devices are manufactured, each lithographic apparatus is commonly associated with a track apparatus, comprising wafer handling devices and pre- and post-processing devices. Such an arrangement forms a lithographic processing cell or “lithocell”. Both the lithographic apparatus and the track apparatus have supervisory control systems which are themselves under the control of a further supervisory control system. Wafers, which may be blank or have already been processed to include one or more process or device layers, are delivered to the lithocell in lots (also referred to as batches) for processing.
A lot is, in general, a group of wafers which are to processed by the lithocell in the same way and is accompanied by two “recipes” which specify the processes to be carried out by the track apparatus and by the lithographic apparatus. The lot size may be arbitrary or determined by the size of carrier used to transport substrates around the fab.
The recipe may include details of the resist coating to be applied, temperature and duration of pre- and post-exposure bakes, details of the pattern to be exposed and the exposure settings for that, developments duration, etc.
A large number of tasks must be performed to complete the recipe for a given batch and there are many possible ways these can be done, as in many cases both the track and lithographic apparatus are capable of performing multiple tasks at once, e.g. if the track apparatus includes multiple spin coaters or multipurpose stations or if the lithographic apparatus is a dual stage apparatus having measurement and exposure stations. Thus scheduling the tasks to be performed, and optimizing that schedule to maximize throughput, is a complex task.
A new approach to scheduling is described in European Patent Application No. 03256456.9 filed 13 Oct. 2003 and U.S. patent application Ser. No. 10/743,320 filed 23 Dec. 2003, which documents are hereby incorporated by reference. The approach described in these documents is model and state-based and may be applied to the whole or parts of a track apparatus unit or a lithographic apparatus as well as to the lithocell as a whole.
In the case where separate control systems and scheduling are provided for the track apparatus and the lithographic apparatus, there is a need for synchronization of the track apparatus and scanner, to ensure that the track apparatus is able to deliver an unexposed resist-coated wafer and receive an exposed wafer as required by the lithographic apparatus. The throughput of wafers, which will generally be greater than 100 wafers per hour, must be maximized to reduce the cost of ownership of the lithographic apparatus, which has a high capital cost. Normally, throughput is limited by the rate at which the lithographic apparatus can expose wafers and the track apparatus is arranged to operate a little faster than the lithographic apparatus so that there is always a prepared wafer waiting to be taken by the lithographic apparatus. A buffer is provided in the track apparatus to accommodate the waiting wafers. However, the present inventors have determined by investigation and experimentation that this approach does not always provide maximum throughput.